Method, apparatus, and system for time synchronization of XDSL

ABSTRACT

The present invention provides a method, an apparatus, and a system for time synchronization of an xDSL. The method includes: transmitting, by a customer premises equipment, a first symbol to a central office equipment, and obtaining time Ts2 indicating the moment that the first symbol is transmitted; receiving, by the CPE, a second symbol transmitted by the CO, and obtaining time Ts1 indicating the moment that the second symbol is received; obtaining, by the CPE obtains time Tm2 indicating the moment that the first symbol is received by the CO and time Tm1 indicating the moment that the second symbol is transmitted by the CO; the CPE calculates an offset between a clock of the CPE and a clock of the CO according to Ts1, Ts2, Tm1 and Tm2; and the CPE adjusts the clock of the CPE according to the offset to achieve synchronization.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/184,276, filed on Jul. 15, 2011, which is a continuation ofInternational Application No. PCT/CN2009/075002, filed on Nov. 18, 2009.The International Application claims priority to the Chinese PatentApplication No. 200910105103.3, filed on Jan. 16, 2009, both of whichare incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present invention relates to the communications field, and moreparticularly, to a method, an apparatus, and a system for timesynchronization of a Digital Subscriber Line (DSL).

BACKGROUND

With emerging of the 3^(rd)-generation (3G) mobile communication andother advanced digital mobile communication technologies, the number ofFemtocell is increasing to meet the requirement. Time synchronizationwith high accuracy is required for the Femtocell. In general, a clockrecovery module is included in a network terminal. Therefore, clocksynchronization (i.e., frequency synchronization) is easily to beprovided for the Femtocell. However, time synchronization is verydifficult to be provided. Some technical issues need to be solved. FIG.1 is a schematic diagram showing a scheme for achieving accurate timesynchronization proposed in the art. Assuming that Offset is an offsetbetween a slave clock and a master clock, Delay1 is a propagation delayfrom the master clock to the slave clock and Delay2 is a propagationdelay from the slave clock to the master clock. Then the following maybe known from FIG. 1 that:Ts0=Tm1+OffsetTs1−Ts0=Delay1then, Offset=Ts1−Tm1−Delay1similarly, Tm2=Ts2−Offset+Delay2so, Offset=Ts2−Tm2+Delay2If the delay from the master clock to the slave clock is equal to thedelay from the slave clock to the master clock, i.e., Delay1=Delay2,thenOffset=(Ts1+Ts2−Tm1−Tm2)/2.  (1)

In this way, the offset between the slave clock and the master clock isobtained so that the slave clock can be synchronized with the masterclock accurately.

However, in the case that an xDigital Subscriber Line (xDSL) deviceworks for mobile backhaul, the Master corresponds to a central office(CO) equipment, and the Slave corresponds to a customer premisesequipment (CPE). The channel between the CO equipment and the CPE iscomplicated, and passes through an analog circuit of the CO equipment, acable, an analog circuit of the CPE and also digital signal processingcircuits at the CO equipment and the CPE. As a result, a downlink delayfrom the CO equipment to the CPE may not necessarily be equal to anuplink delay from the CPE to the CO equipment; i.e., generally, Delay1Delay2. According to some measuring results, the difference betweenDelay1 and Delay2 is more than fps. Therefore, the offset between the COclock and the CPE clock cannot be derived directly with formula (I).

As shown in FIG. 2, a downstream delay includes a delay Δt1 of a COdigital transmitting circuit 70, a delay Δt2 of a CO analog transmittingcircuit 203, a downstream delay Δt3 of a twisted pair 90, a delay Δt2′of a CPE analog receiving circuit 205, and a delay Δt1′ of a CPE digitalreceiving circuit 80; and a upstream delay includes a delay Δt4 of a COdigital receiving circuit 75, a delay Δt5 of a CO analog receivingcircuit 2005, an upstream delay Δt6 of a twisted pair 90, a delay Δt5′of a CPE analog transmitting circuit 2003, and a delay Δt4′ of a CPEdigital transmitting circuit 85. In general,Delay1=Δt1+Δt2+Δt3+Δt2′+Delay2=Δt4+Δt5+Δt6+Δt5′+Δt4′, and the differencebetween the two delays is generally larger than 1 μs.

An xDSL receiver detects a frame boundary and implements framesynchronization during the initialization. In actual cases, a littleerror may exist with the synchronization algorithm, and the precision ofthe synchronization is restricted by the sampling rate and an error ofthe frame synchronization may affect the accuracy of the timesynchronization. If the beginning of a specified frame is recorded as atime stamp Tm1 (at the CO side) or a time stamp Ts2 (at the CPE side) bya transmitter, an error is introduced when a time stamp Ts1 (at the CPEside) or a time stamp Tm2 is recorded by a receiver with an algorithmfor frame synchronization. Due to the error of frame synchronization, anerror introduced by recording the Ts1 at the CPE side or the Tm2 at theCO side will be very large. In particular, the error will be even largerwhen the Tm2 is recorded by the CO in the upstream direction with lowsampling rate.

Delay1 may also be obtained by directly measuring a downstream channeldelay. In this way, an offset between the CO and the CPE can be directlyobtained, i.e., Offset=Ts1−Tm1−Delay1. However, at present, themeasurement of the xDSL channel delay (especially the twisted pair) isnot accurate enough, particularly when loop length is too long, largenoises exist in the loop, or bridging taps exist in the loop.

SUMMARY

Embodiments of the present invention can obtain a delay of a channelaccurately, correct clock time read by CO equipment and by CPE, andachieve time synchronization between the CPE and the CO equipment bycalculating an offset between the clock of the CPE and the clock of theCO equipment.

An embodiment of the present invention provides a method for timesynchronization of a digital subscriber line (DSL). The method includes:

transmitting, by a first apparatus, a first symbol to a secondapparatus, and obtaining time Ts2 indicating the moment that the firstsymbol is transmitted;

receiving, by the first apparatus, a second symbol transmitted by thesecond apparatus, and obtaining time Ts1 indicating the moment that thesecond symbol is received;

obtaining, by the first apparatus, time Tm2 indicating the moment thatthe first symbol is received by the second apparatus and time Tm1indicating the moment that the second symbol is transmitted by thesecond apparatus;

calculating, by the first apparatus, an offset between a clock of thefirst apparatus and a clock of the second apparatus according to Ts1,Ts2, Tm1, Tm2, and a delay of the first apparatus; and adjusting, by thefirst apparatus, the clock of the first apparatus according to theoffset to achieve synchronization.

An embodiment of the present invention provides a DSL apparatus. The DSLapparatus includes:

a transmitting unit, configured to transmit a first symbol and obtaintime Ts2 indicating the moment that the first symbol is transmitted;

a receiving unit, configured to receive a second symbol transmitted by asecond apparatus and obtain time Ts1 indicating the moment that thesecond symbol is received; and

obtain time Tm2 indicating the moment that the first symbol is receivedby the second apparatus and time Tm1 indicating the moment that thesecond symbol is transmitted by the second apparatus;

a processing unit, configured to obtain a delay of the DSL apparatus,calculate an offset between a clock of the DSL apparatus and a clock ofthe second apparatus according to Ts1, Ts2, Tm1, Tm2, and the delay ofthe DSL apparatus, and adjust the clock of the DSL apparatus accordingto the offset.

An embodiment of the present invention provides a system for timesynchronization of a DSL. The system includes a first apparatus and asecond apparatus, where:

the first apparatus transmits a first symbol, and obtains time Ts2indicating the moment that the first symbol is transmitted;

the second apparatus receives the first symbol, and obtains time Ts1indicating the moment that the first symbol is received;

the second apparatus transmits a second symbol, and obtains time Tm1indicating the moment that the second symbol is transmitted;

the first apparatus receives the second symbol, and obtains time Ts1indicating the moment that the second symbol is received;

the second apparatus transmits the time Tm1 and the time Tm2 to thelocal terminal;

the first apparatus calculates an offset between a clock of the firstapparatus and a clock of the second apparatus according to Ts1, Ts2,Tm1, Tm2, and a delay of the first apparatus; and

the first apparatus adjusts the clock of the first apparatus accordingto the offset to achieve synchronization.

According to the embodiments of the present invention, the problem thatan indistinct frame boundary is caused when the frame boundary isrecovered through a receiving terminal algorithm can be solved; asynchronization error between a receiving terminal and a transmittingterminal can be calculated according to a specific symbol transmitted bythe transmitting terminal, and then a time mark error caused by theindistinct frame boundary can be corrected according to thesynchronization error. Meanwhile, an offset between a clock of the CPEand a clock of the CO equipment can be obtained by calculating a delayof a channel so that time synchronization between the clock of the CPEand the clock of the CO equipment can be accurately achieved accordingto the offset.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the principle of timesynchronization defined in IEEE 1588v2;

FIG. 2 is a schematic diagram of a downstream propagation delay and anupstream propagation delay;

FIG. 3 is a flow chart of a synchronizing method according to a firstembodiment of the present invention;

FIG. 4 is a schematic diagram identifying the elements constituting adownstream propagation delay;

FIG. 5 is a schematic diagram identifying the elements constituting anupstream propagation delay;

FIG. 6 is a flowchart of a synchronizing method according to a secondembodiment of the present invention;

FIG. 7 is a schematic diagram of a system according to the presentinvention; and

FIG. 8 is a schematic diagram of an apparatus according to the presentinvention.

DETAILED DESCRIPTION

Hereinafter, the present invention is described clearly with referenceto the accompanying drawings.

A first embodiment of the present invention provides a method for timesynchronization of xDSL. The method includes the following steps:

transmitting, by a first apparatus, a first symbol to a secondapparatus, and obtaining time Ts2 indicating the moment that the firstsymbol is transmitted;

receiving, by the first apparatus, a second symbol transmitted by thesecond apparatus, and obtaining time Ts1 indicating the moment that thesecond symbol is received;

obtaining, by the first apparatus, time Tm2 indicating the moment thatthe first symbol is received by the second apparatus and time Tm1indicating the moment that the second symbol is transmitted by thesecond apparatus;

calculating, by the first apparatus, an offset between a clock of thefirst apparatus and a clock of the second apparatus according to Ts1,Ts2, Tm1, Tm2, and a delay of the first apparatus; and

adjusting, by the first apparatus, the clock of the first apparatusaccording to the offset to achieve synchronization. In the followingembodiments, the first apparatus is taken as a CPE and the secondapparatus is taken as a CO; however, it can be understood by peopleskilled in the art that the first apparatus may also be a CO and thesecond apparatus may also be a CPE.

When an uplink delay is not equal to a downlink delay, the offsetbetween the clock of the CPE and the clock of the CO is obtained byusing a certain mathematic relationship existing between the downstreampropagation delay Delay1 and the upstream propagation delay Delay2 sothat the CPE (or the CO) can adjust the local clock according to thisoffset.

The method for time synchronization according to the first embodimentoperates in such a way that the CPE first transmits a sync symbol andthen the CO transmits a sync symbol, the specific process of which isshown in FIG. 3.

In step 10, the CPE transmits the first symbol, and obtains time Ts2indicating the moment that the first symbol is transmitted.

A discrete multi-carrier (DMT) modulating scheme is used in xDSL so thata signal is transmitted in a DMT frame. In this case timesynchronization in xDSL is also achieved in DMT frames. Therefore, thefirst symbol transmitted by the CPE may be a DMT frame, and the specificframe to be chosen is determined through negotiation between the CPE andthe CO.

During the initialization, the CPE transmits the first symbol. When acertain position of the first symbol is written into a buffer or a D/Amodule from the buffer, the CPE records the corresponding time Ts2 ofits local clock.

A certain point at which a time stamp is triggered to record is alsodetermined through negotiation between the CO and the CPE. Any positionin the first symbol may be used. In the following embodiments, abeginning position of the first symbol is taken as an example.

In step 20, the CO receives the first symbol transmitted by the CPE, andobtains time Tm2 indicating the moment that the first symbol isreceived.

The CO receives the first symbol transmitted by the CPE. When the COwrites a sample at the beginning position of the first symbol into thebuffer or the sample at the beginning position of the first symbol isread by an A/D module from the buffer, the CO records the correspondingtime Tm2′ of its local clock, (i.e., an action is triggered to obtain atime stamp). Because the CO obtains a frame boundary by calculating witha certain algorithm, an error may be introduced when the beginningposition is calculated with the algorithm. In this case, the time Tm2′needs to be corrected by the CO.

According to a phase difference between a receiving point phase and acheck point phase of a sinusoidal signal (or a cosinoidal signal) of thefirst symbol, the CO corrects the time Tm2′ to a time Tm2 wherein thetime Tm2 is the time indicating the moment that the check point shouldbe received by the CO. The receiving point is a signal point where thefirst symbol is initially received by the CO, and the check point is asignal point where the first symbol is initially transmitted by the CPE.

When the CO corrects the time Tm2′ according to a sinusoidal signal inthe first symbol:

a phase of a corresponding point in the sinusoidal signal is fixed (forexample, 0°, 45°, 90°, or any other angle) when an action to obtain thetime stamp is triggered by the CPE so that this point may be taken as acheck point and the phase of the check point is obtained when COcorrects the time Tm2′. In the following embodiments, 0° is taken as anexample.

The CO obtains a position of the sinusoidal signal where the CO triggersto obtain a time stamp, where the position is a receiving point wherethe first symbol is received by the CO, and calculates the time thatneeds to be taken from the phase of the receiving point to the phase ofthe check point. Then according to the time, the CO adjusts the timeTm2′ to the time Tm2.

The CO may also make the correction by using a plurality of sinusoidalsignals in the symbol. When the CPE writes the sample at the beginningposition of the first symbol into the buffer or the sample at thebeginning position of the first symbol is read from the buffer, each ofthe sinusoidal signals in the first symbol is just at a specific point.The CO takes these points as check points and knows respective phases ofthe check points in the sinusoidal signals when the CPE takes the timestamps. For example, a checkpoint in one of the sinusoidal signals is at0°, one checkpoint is at 90°, one check point is at 45°, and so on.

After receiving the first symbol, the CO obtains a correspondingreceiving point from each of the sinusoidal signals, and obtains thephase of the receiving point. Then, the CO calculates the time takenfrom the phase of the receiving point to the phase of the check point.The time is an offset of a time stamp made by the CO in each of thesinusoidal signals. The phases of these sinusoidal signals can beobtained through the fast Fourier transform (FFT) in the DMT system. Inorder to improve estimation accuracy and reduce influence of noises, theoffset can be the average of the multiple calculations, or estimatedwith the FEQ coefficient of a trained frequency domain equalizer (FEQ)following the FFT because the compensation of the angle offset can bemade by the FEQ. Because an error may be introduced during the DMT framesynchronization there may be an offset between these angles obtained bythe CO and the CPE. The offset have a linear relationship withfrequencies of the sinusoidal signals, and the slope of the linearrelationship directly reflects the frame synchronization error. Theoffset of each of the sinusoidal signals can be plotted on a coordinatesystem, and then these offsets are connected by a beeline. The slope ofthe beeline is just the offset of time stamp taken by the CO due to thesynchronization error. Affected by such factors as noises, these angleerrors obtained through actual calculation may not be strictly on abeeline. The CO can obtain an optimal beeline for approximationaccording to a certain optimization algorithm (for example, the leastsquare method) so that the CO can calculate the error of time stampstaken at the far end and corrects the time stamp Tm2′ to the time stampTm2 according to this error.

Considering the features of the xDSL system, these angle errors may alsobe obtained by using FEQ information, and then the time Tm2′ is adjustedto the time Tm2 in a similar way.

In step 30, the CO transmits a second symbol, and obtains time Tm1indicating the moment that the second symbol is transmitted.

The CO transmits a second symbol, which may also be a DMT frame. Whenthe CO writes a sample at a beginning position of the second symbol intothe buffer or a sample at the beginning position of the second symbol isread from the buffer by a D/A module of the CO, a time value of a localclock at the CO side is taken by the CO (i.e., an action is triggered toobtain the time stamps) and obtains the time Tm1. A specific point, atwhich the action to obtain the time is triggered, is also determinedthrough negotiation between the CO and the CPE, and any position of thesecond symbol may be used as a specific point. In the followingembodiments, the beginning position of the second symbol is taken as anexample.

In step 40, the CPE receives the second symbol transmitted by the CO,and obtains exact time Ts1 indicating the moment that the second symbolis received.

When the sample at the beginning position of the second symbol iswritten into the buffer or read from the buffer by an A/D module, theCPE triggers an action to obtain the time stamps and records the timevalue of the local clock at the CPE side as time Ts1′. Because the CPEalso calculates the frame boundary by means of a certain algorithm, anerror may be introduced in determining the beginning position of thesecond symbol, and the obtained time Ts1′ also needs to be corrected bythe CPE.

According to a phase difference between a receiving point phase and acheckpoint phase of a sinusoidal signal (or a cosinoidal signal) in thesecond symbol, the CPE corrects the time stamp Ts1′ to the time stampTs1 wherein the time stamp Ts1 is the time indicating the moment thatthe check point should be received. The receiving point is a signalpoint where the second symbol is initially received by the CPE, and thecheck point is a signal point where the second symbol is initiallytransmitted by the CO.

When the CPE uses one sinusoidal signal in the second symbol, a phase ofa corresponding point in this sinusoidal signal is fixed when the COtriggers the action to record the time stamp, so this point in thesinusoidal signal can be taken as a check point and a phase of the pointis obtained, for example 0°. Therefore, the CPE may make a correctionaccording to this check point.

The CPE takes the corresponding point of the sinusoidal signalindicating the moment that the second symbol is received by the CPE asthe receiving point, and obtains a phase of this point. Then, the CPEcalculates the time taken from this phase to a phase of a nearest checkpoint, and adjusts the time Ts1′ to the time Ts1 according to the time.

The CPE may also use a plurality of sinusoidal signals in the secondsymbol. The CPE has known the phases of the corresponding points ofthese sinusoidal signals when the CO makes the time marks; for example,a corresponding point of one of the sinusoidal signals is at 0°, one isat 90°, one is at 45°, and so on. Therefore, the CPE may take thecorresponding point of each sinusoidal signal as a check point. Afterreceiving the second symbol, the CPE obtains the position where the CPEmakes a time mark on each of the sinusoidal signals and takes thesepoints as receiving points. Then, the CPE calculates time taken from thephase of a receiving point to the phase of a check point. The time isjust an offset of the time mark made by the CPE in each of thesinusoidal signals. Angles of these sinusoidal signals can be obtainedthrough the FFT in the DMT system. In order to improve estimationaccuracy and reduce influence of noises, the offset can be obtainedthrough averaging after multiple calculations or through training afrequency domain equalizer (FEQ) after the FFT. Because the FEQ makescompensation for the angle offset, the trained FEQ coefficient may alsobe used to estimate the angle offset of each of the sinusoidal signals.Because the DMT frame synchronization may have an error, there may beoffsets between these angles obtained by the CPE and the CO. Theseoffsets have a linear relationship with frequencies of the sinusoidalsignals, and a slope of the linear relationship directly reflects theframe synchronization error. The offset of each of the sinusoidalsignals can be plotted on a coordinate system, and these offsets areconnected by a beeline; and a slope of the beeline is just the offset ofthe time marks made by the CPE due to the synchronization error.Affected by such factors as noises, these angle errors obtained throughactual calculation may not be strictly on a beeline. Accordingly, theCPE can calculate an optimal beeline for approximation according to acertain optimization algorithm (for example, the least square method).Therefore, the CPE calculates the offset of the time marks made by theCPE and corrects the time Ts1′ to the time Ts1 according to the offset.

In step 50, the CPE obtains time Tm2 and time Tm1 of the CO.

The CO transmits the time Tm1 and Tm2 to the CPE via a message channel.

The CPE obtains a propagation delay of the CO and a propagation delay ofthe CPE.

A propagation delay from the CO to the CPE is shown in FIG. 4 andincludes:

(1) a delay of a CO digital transmitting circuit denoted by Δt1, whichincludes a delay of a BUF 201 and a delay of a D/A 202; and a delay of aCPE digital receiving circuit denoted by Δt1′, which includes a delay ofa BUF 207 and a delay of a D/A 206. In some systems, the delays Δt1 andΔt1′ are fixed and can be read directly from the equipment. Incalculation of the delay, both delays shall be included. In some othersystems, the delays Δt1 and Δt1′ are not fixed, so they shall beexcluded during calculation. It may also be possible that part of bothdelays is fixed, and then during calculation, only the fixed part ofdelay is included;

(2) a delay of a CO analog transmitting circuit 203 denoted by Δt2 and adelay of a CPE analog receiving circuit 205 denoted by Δt2′. Both of thedelays Δt2 and Δt2′ occur on the devices, and can be obtained in thefactory or through information exchange between the CPE and the CO; and

(3) a delay of a symbol on a twisted pair 204 from the CO to the CPEdenoted by Δt3, which is unknown.

A propagation delay from the CPE to the CO is shown in FIG. 5 andincludes:

(1) a delay of a CPE digital transmitting circuit denoted by Δt4, whichincludes a delay of a CPE BUF 2001 and a delay of a CPE D/A 2002; and adelay of a CO digital receiving circuit denoted by Δt4′, which includesa delay of a CO D/A 2006 and a delay of a BUF 2007. In some systems,both of the delays Δt4 and Δt4′ are fixed and can be read directly fromthe equipment. In some other systems, both of the delays are not fixed,and then during calculation, both of the delays are not included;

(2) a delay of a CPE analog transmitting circuit 2003 denoted by Δt5 anda delay of a CO analog receiving circuit 2005 denoted by Δt5′. Becauseboth of the delays Δt5 and Δt5′ occur on the devices, they can beobtained in the factory or through information exchange between the COand the CPE; and

(3) a delay of a signal on a twisted pair 2004 from the CPE to the COdenoted by Δt6, which is unknown.

The CO transmits the delays Δt1, Δt2, Δt4′, and Δt5′ to the CPE via amessage channel, or pre-stored data is obtained by the CPE.

In step 60, the CPE calculates an offset between a clock of the CPE anda clock of the CO, and adjusts the clock of the CPE according to theoffset.

The CPE calculates the offset between the clock of the CPE and the clockof the CO according to:Offset=Ts1−Tm2−Delay1, andOffset=Tm2−Ts2+Delay2.

During the calculation process, the CPE establishes a calculation modeland splits Delay1 and Delay2. The CPE stores the mathematic relationshipbetween Delay1 and Delay2, for example, the proportion of Δt3=0.9Δt6 orΔt6=0.9Δt3. The proportion can be obtained through statistics. TheOffset can be obtained with the following equations:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt1+Δt2+Δt3+Δt1′+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt4+Δt5+Δt6+Δt5′+Δt4′)orOffset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt2+Δt3+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt5+Δt6+Δt5′)

The delays Δt3 and Δt6 are approximately identical or have a proportionrelationship. Assume that the delays Δt3 and Δt6 are approximatelyidentical. The Offset can be estimated by the following equation:Offset=(Ts1−Tm1−(Δt1+Δt2+Δt1′+Δt2′)+Ts2−Tm2+(Δt4+Δt5+Δt4′+Δt5′))/2orOffset=(Ts1−Tm1−(Δt2+Δt2′)+Ts2−Tm2+(Δt5+Δt5′))/2

The delays Delay1 and Delay2 can be obtained with the estimated Offset:Delay1=Ts1−Tm1−OffsetDelay2=Ts2−Tm2+Offset

After having obtained the offset between the clock of the CPE and theclock of the CO, the CPE obtains the time value of the local clock andadjusts the time of local clock according to the obtained local clocktime and the offset.

In the above embodiments, the CPE first transmits a symbol, and then theCO receives the symbol and further transmits a symbol. In the actualmonitoring process, it is also feasible that the CO transmits a symboland then the CPE receives the symbol and further transmits a symbol. Thelatter case will be described in the following second embodiment, aspecific process of which is shown in FIG. 6.

In step 15, the CO transmits a second symbol, and obtains time Tm1indicating the moment that the second symbol is transmitted.

During the initialization, the CO transmits a second symbol. When asample at a specific position of the second symbol is written into abuffer by the CO or read from the buffer by a D/A module of the CO, anaction of obtaining time stamps is triggered to read a time value of alocal clock of the CO and obtain a time stamp Tm1. The second symbol maybe a DMT frame. A specific point, at which the action of obtaining timestamps is triggered, is also determined through negotiation between theCO and the CPE. Any position in the second symbol may be used as aspecific point. Hereinafter, a beginning position of the second symbolis taken as an example in this embodiment.

In step 25, the CPE receives the second symbol transmitted by the CO,and obtains exact time Ts1 indicating the moment that the second symbolis received.

When a sample at the beginning position of the second symbol is writteninto the buffer by the CPE or read from the buffer by an A/D module, anaction of obtaining time stamps is triggered to obtain a time value ofthe local clock of the CPE denoted by Ts1′. Because the CPE calculates aframe boundary by means of a certain algorithm, an error may beintroduced when the beginning position is calculated by means of thealgorithm. In this case, the time Ts1′ needs to be corrected by the CPE.The correction method used here is the same as that of the CPE in thefirst embodiment.

In step 35, the CPE transmits a first symbol, and obtains time Ts2indicating the moment that the first symbol is transmitted by the CPE.

During the initialization, the CPE transmits a first symbol, which mayalso be a DMT frame. When a sample at a specific position of the firstsymbol is written into the buffer or read from the buffer by a D/Amodule, an action of obtaining time stamps is trigged by the CPE to reada time value of the local clock of the CPE denoted by Ts2. A specificpoint, at which the action of obtaining time stamps is triggered, isalso determined through negotiation between the CO and the CPE. Anyposition in the first symbol may be used. Hereinafter, a beginningposition of the first symbol is taken as an example in this embodiment.

In step 45, the CO receives the first symbol transmitted by the CPE, andobtains exact time Tm2 indicating the moment that the first symbol isreceived.

The CO receives the first symbol transmitted by the CPE. When a sampleat the beginning position of the first symbol is written into the bufferor read from the buffer by an A/D module, an action of obtaining timestamps is triggered to read a time value of a local clock of CO denotedby Tm2′. Because the CO calculates a frame boundary by means of acertain algorithm, the time stamp Tm2′ needs to be corrected by the CO.The correction method used herein is to the same as that of the CO inthe first embodiment.

In step 55, the CPE obtains the time Tm1 and Tm2 obtained by the CO.

The CO transmits the time Tm1 and Tm2 to the CPE via a message channel.

The CPE obtains a delay of the CO and a delay of the CPE:

(1) a delay of the CO digital transmitting circuit denoted by Δt1, whichincludes a delay of a CO BUF 201 and a delay of a D/A 202; and a delayof the CPE digital receiving circuit denoted by Δt1′, which includes adelay of a CPE BUF 207 and a delay of a D/A 206. In some systems, bothof the delay are fixed and can be read directly from the equipment. Incalculation of the propagation delay, both of the delays shall beincluded. In some other systems, both of the delay are not fixed, sothey shall be excluded during calculation. It may also be possible thatpart of the two delays is fixed, and then during calculation, only thefixed part is included;

(2) a delay of a CO analog transmitting circuit 203 denoted by Δt2 and adelay of a CPE analog receiving circuit 205 denoted by Δt2′. The delayst2 and Δt2′ both occur in the equipment, and can be obtained in thefactory or through information exchange between the CPE and the CO;

(3) a delay of a symbol on a twisted pair 204 from the CO to the CPEdenoted by Δt3, which is unknown.

A propagation delay from the CPE to the CO is shown in FIG. 5 andincludes:

(1) a delay of the CPE digital transmitting circuit denoted by Δt4,which includes a delay of a CPE BUF 2001 and a delay of a CPE D/A 2002;and a delay of the CO digital receiving circuit denoted by Δt4′, whichincludes a delay of a CO D/A 2006 and a delay of a BUF 2007. In somesystems, both of the delays are fixed and can be read directly from theequipment. In some other systems, both of the delays are not fixed, andthen during calculation, the two delays are not included;

(2) a delay of a CPE analog transmitting circuit 2003 denoted by Δt5 anda delay of a CO analog receiving circuit 2005 denoted by Δt5′. Becausethe delays Δt5 and Δt5′ both occur on the devices, they can be obtainedin the factory or through information exchange between the CO and theCPE;

(3) a delay of a signal on a twisted pair 2004 from the CPE to the COdenoted by Δt6, which is unknown.

The CO transmits the delays Δt1, Δt2, Δt4′, and Δt5 to the CPE via amessage channel; or alternatively, the CPE obtains pre-stored data andthus the CO may also not transmit the information.

In step 65, the CPE calculates an offset between a clock of the CPE anda clock of the CO Offset, and adjusts the time of the CPE clockaccording to this offset.

The CPE calculates the offset according to the following equations:Offset=Ts1−Tm2−Delay1, andOffset=Ts2−Tm2+Delay2.

During the calculation process, the CPE establishes a calculation modeland splits Delay1 and Delay2. The CPE stores the mathematic relationshipbetween Delay1 and Delay2, for example, the proportion of Δt3=0.96t6 orΔt6=0.9Δt3. The specific mathematic relationship can be obtained throughstatistics. The Offset is obtained with the following equations:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt1+Δt2+Δt3+Δt1′+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt4+Δt5+Δt6+Δt5′+Δt4′)orOffset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt2+Δt3+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt5+Δt6+Δt5′)

Because the delays Δt3 and Δt6 are approximately identical or have aproportion relationship, the Offset can be estimated.

After the Offset is obtained, the related delays Delay1 and Delay2 canbe obtained:Delay1=Ts1−Tm1−OffsetDelay2=Ts2−Tm2+Offset

After having obtained the offset between the clock of the CPE and theclock of the CO, the CPE obtains a time of the local clock of the CPE,and adjusts the time of the local clock according to the obtained localclock time and the estimated offset.

A third embodiment of the present invention provides a method for timesynchronization of an xDSL. The method is applicable to the case thatthe delays Delay1 and Delay2 can be obtained by means of SELT or DELT orother ways. The method includes the following steps.

In step 1, the CO transmits a symbol, and obtains time Tm1 indicatingthe moment that the symbol is transmitted (or the CPE transmits asymbol, and obtains time Ts2 indicating the moment that the symbol istransmitted), and this symbol may be a DMT frame.

In an initialization stage, the CO transmits the symbol. When the COwrites data sampled at a specific position of this symbol into a bufferor a D/A module of the CO reads the data sampled at the specificposition of this symbol from the buffer, the CO triggers a time markingaction, reads local clock time of the CO and obtains the time Tm1. Aspecific point, at which the time marking action is triggered, is alsodetermined through negotiation between the CO and the CPE, and anyposition in this symbol may be used. Hereinafter, a starting position ofthis symbol is taken as an example in this embodiment.

In step 2, the CPE receives the symbol transmitted by the CO, andobtains receiving time Ts1 (or the CO receives the symbol transmitted bythe CPE, and obtains time Tm2 indicating the moment that this symbol isreceived).

When the CPE writes data sampled at the starting position of this symbolinto the buffer or an A/D module reads the data sampled at the startingposition of this symbol from the buffer, the CPE triggers the timemarking action and reads the local time Ts1′ of the CPE. Because the CPEcalculates a frame boundary by means of a certain algorithm, thestarting position calculated by means of the algorithm may have anerror. In this case, the time Ts1′ needs to be corrected by the CPE. Thecorrection method is the same as that of the CPE in the firstembodiment.

In step 3, the CPE obtains the time Tm1 transmitted by the CO (or theCPE obtains the time Tm2 transmitted by the CO).

The CO transmits the time Tm1 (or the time Tm2) to the CPE via a messagechannel.

In step 4, the CPE calculates an offset between a clock of the CPE and aclock of the CO according to Offset=Ts1−Tm1−Delay1 orOffset=Ts2−Tm2+Delay2.

Because Delay1 (or Delay2) has been measured, the offset can be solved.

In step 4, the CPE obtains a time value of the local clock, and adjuststhe time of the local clock according to the obtained time of the localclock and the offset.

A fourth embodiment of the present invention provides a method for timesynchronization of a DSL. Because a delay exists due to the processingof the equipment, the delay of equipment should be taken into accountwhen the propagation delay of a symbol is calculated. In this way, thedelay of CO equipment may not be needed when Offset is calculated by theCPE. Specific steps are as follows:

In a first step, the CO transmits a second symbol, and obtains timeindicating the moment that the second symbol is transmitted.

During the initialization, when a sample at a beginning position of thesecond symbol is written into a buffer by the CO or read from the bufferby the CO, an action of obtaining time stamps is triggered to read thetime of the local clock Tm1.

The CO equipment obtains a CO digital transmitting delay Δt1 and ananalog transmitting delay Δt2, and processes the time when the secondsymbol is transmitted by the CO equipment. Specifically,Tm1=Tm1+Δt1+Δt2; and if the digital transmitting delay is not fixed, itcan be excluded and in this case, Tm1=Tm1+Δt2.

In a second step, the CPE receives the second symbol, and obtains timeindicating the moment that the second symbol is received by the CPE.

When a sample at the beginning position of the second symbol is writteninto the buffer by CPE or read from the buffer by an A/D module, anaction of obtaining time stamps is triggered by the CPE to read a timevalue of the local clock of the CPE denoted by Ts1′. Because the CPEcalculates a frame boundary by means of a certain algorithm, an errormay be introduced when the beginning position is calculated by means ofthe algorithm. In this case, the time Ts1′ needs to be corrected by theCPE, and the correction method used herein is the same as that of theCPE in the first embodiment.

In a third step, the CPE transmits a first symbol, and obtains timeindicating the moment that the first symbol is transmitted.

During the initialization, the CPE transmits the first symbol. When asample at a specific position of the first symbol is written into thebuffer by the CPE or read a sample at the specific position of thissymbol from the buffer by a D/A module, an action of obtaining timestamps is triggered to read the time of the local clock Ts2.

In a fourth step, the CO receives the first symbol, and obtains timeindicating the moment that the first symbol is received.

The CO receives the first symbol transmitted by the CPE. When a sampleat a beginning position of the first symbol is written into the bufferby the CO or read a sample at the specific position of this symbol fromthe buffer by an A/D module, an action of obtaining time stamps istriggered to read the time value of the local clock Tm2′. Because the COcalculates the frame boundary by means of a certain algorithm, an errormay be introduced when the beginning position is calculated by means ofthe algorithm. In this case, the read time Tm2′ needs to be corrected bythe CO, and the correction method used here is the same as that in thefirst embodiment.

A specific point, at which the action of obtaining time stamps istriggered, is determined through negotiation between the CO and the CPE.Any position in the first symbol may be used, for example, the beginningposition of the first symbol.

The CO obtains a delay of the CO digital receiving circuit denoted byΔt4 and a delay of the analog receiving circuit denoted by Δt5, andprocesses the time stamps indicating the moment that the first symbol isreceived by the CO equipment. Specifically, Tm2=Tm2−Δt4−Δt5. If thedigital receiving delay is not fixed, it can be excluded and thereforeTm2=Tm2−Δt5.

In a fifth step, the CO transmits the time Tm1 and the time Tm2 to theCPE via a message channel, and the CPE calculates an offset between aclock of the CPE and a clock of the CO.

The CPE obtains a delay of the digital receiving circuit Δt1′, a delayof an analog receiving circuit Δt2′, a delay of the digital transmittingcircuit Δt4′, and a delay of the analog transmitting circuit Δt5′ of theCPE.

The CPE calculates the offset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt1′+Δt2′+Δt3),andOffset=Ts2−Tm2+Delay1=Ts2−Tm2+(Δt4′+Δt5′+Δt6).

Alternatively, the digital receiving delay and the digital transmittingdelay are not fixed and thus excluded, and then the CPE calculates theoffset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt2′+Δt3), andOffset=Ts2−Tm2+Delay1=Ts2−Tm2+(Δt5′+Δt6).

In this process, the CPE may also process the time stamp Ts2 indicatingthe moment the second symbol transmitted and the time stamp Ts1indicating the moment the first symbol received. For example,Ts1=Ts1−Δt1′−Δt2′ or Ts1=Ts1−Δt2′; Ts2=Ts2−t4′−Δt5′ or Ts2=Ts2−Δt5′. Inthis way, the CPE calculates the offset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−Δt3, andOffset=Ts2−Tm2+Delay1=Ts2−Tm2+Δt6.

The offset is estimated based on the proportion between Δt3 and Δt6 orthe assumption that the delays Δt3 and Δt6 are approximately identical.

In a sixth step, the CPE adjusts the clock of the CPE according to theoffset.

The CPE obtains the time value of the local clock, and adjusts the timeof the local clock according to the obtained local lock time and theestimated offset.

In the above embodiments, it is the CPE that adjusts the local clock ofCPE so that the clock of the CPE is synchronized with the clock of theCO. In practice, the CO may also adjust the local clock of CO so thatthe local clock of the CO is synchronized with the clock of the CPE, inwhich case the synchronization method is similar to the synchronizationmethod in which the CPE adjusts the local clock.

The method described in the above embodiments takes the influence of thesampling rate into account, and can be executed for a plurality oftimes.

An embodiment of the present invention provides an xDSL communicationsystem. As shown in FIG. 7, the communication system includes a CO 100and a CPE 200.

The CPE 200 transmits a symbol, and obtains time Ts2 indicating themoment that the first symbol is transmitted. The CPE 200 transmits thefirst symbol, which is a DMT frame determined through negotiationbetween the CO 100 and the CPE 200 in an initialization stage. The CO100 and the CPE 200 determine through negotiation a point in the firstsymbol as a reference point, which may be at any position in the firstsymbol. Hereinafter, a starting position of the first symbol is taken asan example.

When the CPE 200 writes data sampled at the starting position of thefirst symbol into a buffer or reads the data sampled at the startingposition from the buffer, the CPE 200 triggers an action of obtainingtime stamps and reads the time value of the local clock time Ts2 of theCPE 200.

The CO 100 receives the first symbol transmitted by the CPE 200, andobtains time Tm2 indicating the moment that the first symbol isreceived. When the CO 100 writes the data sampled at the startingposition of the first symbol into the buffer or reads the data sampledat the starting position of the first symbol from the buffer, the CO 100triggers the action of obtaining time stamps and reads the time value ofthe local clock time Tm2′. Because the CO 100 recovers a frame boundaryby using a certain algorithm, an error may occur when the startingposition of the first symbol is determined, and therefore the time needsto be corrected by the CO 100.

According to a phase difference between a receiving point phase and acheck point phase of a sinusoidal signal (or a cosinoidal signal) in thefirst symbol, the CO 100 corrects the time stamp Tm2′ to the time stampTm2 indicating the moment that the CO 100 shall receive a check point.The receiving point is a signal point where the first symbol isinitially received by the CO 100, and the aforesaid check point is asignal point where the first symbol is initially transmitted by the CPE200.

When the CO 100 corrects the time Tm2′ according to one sinusoidalsignal in the first symbol:

a phase of a corresponding point of this sinusoidal signal is fixed (forexample, 0°, 45°, 90° or any other angle) when the CPE 200 triggers toobtain a time stamp, so during the correction process, the CO 100 maytake this point as a check point and obtain a phase of the check point.In the following embodiments, 0° is taken as an example.

The CO 100 obtains a position in this sinusoidal signal where the CO 100triggers to obtain the time stamp (which position is a receiving pointwhere the first symbol is received by the CO 100), and calculates timetaken from the phase of the receiving point to the phase of the checkpoint. Then, the CO 100 adjusts the time Tm2′ into the time Tm2according to the time.

The CO 100 may also carry out the correction by using a plurality ofsinusoidal signals in this symbol. When the CPE 200 writes the startingposition of the first symbol into the buffer or reads the startingposition of the first symbol from the buffer, each of the sinusoidalsignals in the first symbol is at a specific point. The CO 100 takesthese points as check points, and knows respective phases of the checkpoints in these sinusoidal signals when the CPE 200 made time stamps.For example, a check point in one of the sinusoidal signals is at 0°;one is at 90°; one is at 45°; and so on.

After receiving the first symbol, the CO 100 obtains the correspondingreceiving point in each of the sinusoidal signals, and obtains the phaseof the receiving point. Then, the CO 100 calculates time taken from thephase of the receiving point to the phase of the check point. The timeis an offset of the time mark made by the CO 100 in each of thesinusoidal signals. The phases of these sinusoidal signals can beobtained through the FFT in the DMT system. In order to improveestimation accuracy and reduce influence of noises, the offset can beobtained through averaging after multiple calculations or throughtraining a FEQ after the FFT. Because the FEQ makes compensation for anangle offset, the trained FEQ coefficient may also be used to estimatethe angle offset of each of the sinusoidal signals. Because the DMTframe synchronization may have an error, there may be offsets betweenthese angles obtained by the CO 100 and the CPE 200. These offsets havea linear relationship with frequencies of the sinusoidal signals, and aslope of the linear relationship directly reflects the framesynchronization error. The offset of each of the sinusoidal signals canbe drawn on a coordinate, and these offsets are connected by a beeline;and a slope of the beeline is just the offset of the time stamps made bythe CO 100 due to the synchronization error. Affected by such factors asnoises, these angle errors obtained through actual calculation may notbe strictly on a beeline. Accordingly, the CO 100 can calculate anoptimal beeline for approximation according to a certain optimizationalgorithm (for example, the least square method). Therefore, the CO 100calculates the error of the time stamps made by the CPE and corrects thetime Tm2′ to the time Tm2 according to this error.

Considering features of the xDSL system, these angle errors may also beobtained by using FEQ information, and then the time Tm2′ is adjustedinto the time Tm2 in a similar way.

The CO 100 transmits a second symbol, and obtains time Tm1 indicatingthe moment that the second symbol is transmitted. When the CO 100 writesdata sampled at a starting position of the second symbol into a bufferor reads the data sampled at the starting position from the buffer, theCO 100 triggers an action of obtaining time stamps and reads the timevalue of the local clock time Tm1 of the CO 100. A specific point, atwhich the action of obtaining time stamps is triggered, is alsodetermined through negotiation between the CO and the CPE, and anyposition in the second symbol may be used. In this embodiment, thestarting position of the second symbol is taken as an example.

The CPE 200 receives the second symbol transmitted by the CO 100, andobtains time Ts1 indicating the moment that the second symbol isreceived. When the CPE 200 writes the data sampled at the startingposition of the second symbol into the buffer or reads the data sampledat the starting position of the second symbol from the buffer, the CPE200 triggers the action of obtaining time stamps and reads the timevalue of the local clock time Ts1′. Because the CPE 200 recovers a frameboundary by means of a certain algorithm, the CPE 200 corrects the timeTs1′ to the time Ts1 in the same way as that of the CO 100.

The CO 100 transmits the time Tm1 and the time Tm2 to the CPE 200 via amessage channel. If the CPE 200 does not store transmission delay andreception delay of the CO 100, the CO 100 transmits, through interactionwith the CPE 200, the transmission delay and the reception delay of theCO 100 to the CPE 200 via the message channel.

The transmitting delay and the receiving delay of the CO 100 includes adelay Δt1 of the digital transmitting circuit, a delay Δt2 of the analogtransmitting circuit, a delay Δt5′ of the analog receiving circuit, anda delay Δt4′ of the digital receiving circuit.

The CPE 200 obtains the transmission delay and the reception delay ofthe CPE 200, which include a delay Δt1′ of the digital transmittingcircuit, a delay Δt2′ of the analog transmitting circuit, a delay Δt5 ofthe analog receiving circuit, and a delay Δt4 of the digital receivingcircuit. These delays can be read directly from the CPE 200.

The CPE 200 calculates an offset between a clock of the CPE 200 and aclock of the CO 100 according to Ts1, Ts2, Tm1, Tm2, the delay of the CO100, and the delay of the CPE 200.

Specifically, the CPE 200 calculates the offset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt1+Δt2+Δt3+Δt1′+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt4+Δt5+Δt6+Δt5′+Δt4′)orOffset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt2+Δt3+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt5+Δt6+Δt5′),

wherein the CPE 200 stores therein the mathematic relationship betweenthe delay Delay1 and the delay Delay2. Specifically, it can be knownthrough statistics that the delay Δt3 and the delay Δt6 areapproximately equal to each other or have a ratio relationship, forexample, Δt3=0.9Δt6 or Δt6=0.9Δt3.

After obtaining the offset, the CPE 200 obtains a time value of thelocal clock, and adjusts the local clock time according to the obtainedlocal clock time and the offset.

In the above communication system, it is the CPE 200 that adjusts thelocal clock time so that the local clock of the CPE 200 is synchronizedwith the clock of the CO 100. Alternatively, the CO 100 may also adjustthe clock of the CO 100 so that the clock of the CPE 200 is synchronizedwith the clock of the CO 100, the synchronization process of which isthe same as the synchronization process in which the clock of the CPE200 is adjusted.

The present invention further provides an xDSL apparatus, which can beused for the CO and the CPE. As shown in FIG. 8, the apparatus includesa transmitting unit 300, a receiving unit 400 and a processing unit 600.

The transmitting unit is configured to transmit a first symbol andobtain time Ts2 indicating the moment that the first symbol istransmitted.

The receiving unit is configured to receive a second symbol transmittedby a second apparatus and obtain time Ts1 indicating the moment that thesecond symbol is received; and obtain time Tm2 indicating the momentthat the first symbol is received by the second apparatus and time Tm1indicating the moment that the second symbol is transmitted by thesecond apparatus.

The processing unit is configured to obtain a delay of the DSLapparatus, calculate an offset between a clock of the DSL apparatus anda clock of the second apparatus according to Ts1, Ts2, Tm1, Tm2, and thedelay of the DSL apparatus, and adjust the clock of the DSL apparatusaccording to the offset.

Specifically, the transmitting unit 300 transmits the first symbol, andobtains the time Ts2 indicating the moment that the first symbol istransmitted. The first symbol may be a training signal transmittedduring an initialization stage, and this signal may be a DMT frame.

When the transmitting unit 300 writes data sampled at a startingposition of the first symbol into a buffer or reads the data sampled atthe starting position of the first symbol from the buffer, thetransmitting unit 300 triggers an action of obtaining time stamps andreads the local time Ts2.

The receiving unit 400 receives the second symbol transmitted by theopposite terminal and obtains the time Ts1 indicating the moment thatthe second symbol is received. The second symbol may be a trainingsignal transmitted during the initialization stage.

The receiving unit 400 further includes an obtaining module and acorrecting module. The obtaining module receives the second symbol,obtains time Ts1′ of the clock of the DSL apparatus, and obtains thetime Tm2 indicating the moment that the first symbol is received by thesecond apparatus and the time Tm1 indicating the moment that the secondsymbol is transmitted by the second apparatus.

The correcting module, according to a phase difference between areceiving point phase and a check point phase of a signal in the secondsymbol, corrects the time stamp Ts1′ to the time stamp Ts1 indicatingthe moment that the obtaining module shall receive a check point, andobtains the time stamp Ts1 for use as time indicating the moment thatthe second symbol is received by the obtaining module. The receivingpoint is a signal point where the second symbol is initially received bythe obtaining module, and the check point is a signal point where thesecond symbol is initially transmitted by the second apparatus.

When the obtaining module writes data sampled at a starting position ofthe second symbol into the buffer or reads the data sampled at thestarting position of the second symbol from the buffer, the obtainingmodule triggers an action of obtaining time stamps and reads the timevalue of the local clock time Ts1′. Because a boundary of the secondsymbol is recovered by means of a certain algorithm, an error may occurwhen the boundary is positioned. Accordingly, the correcting module,according to a phase difference between a receiving point phase and acheck point phase of a signal in the second symbol, corrects the timestamp Ts1′ to the time stamp Ts1 indicating the moment that theobtaining module shall receive a check point.

The correcting module obtains a position in a sinusoidal signal wherethe module triggers to obtain the time stamp, takes this position as areceiving point, and calculates time taken from the phase of thereceiving point to the phase of the check point. Then according to thetime, the correcting module corrects the time Ts1′ into the time Ts1.

The correcting module may also use a plurality of sinusoidal signals inthe second symbol. The correcting module knows respective angles of thecorresponding points (i.e., the check points) in these sinusoidalsignals when the second apparatus makes time stamps. For example, acheck point in one of the sinusoidal signals is at 0°; one is at 90°;one is at 45°; and so on. Hence, after the second symbol is received bythe obtaining module, the correcting module obtains the positions wherethe obtaining module makes the time stamps, which are receiving points,and calculates the time taken from the phase of each of the receivingpoints to the phase of a corresponding check point. The angles of thesesinusoidal signals can be obtained through the FFT in the DMT system. Inorder to improve estimation accuracy and reduce influence of noises, theoffset can be obtained through averaging after multiple calculations orthrough training a FEQ after the FFT. Because the FEQ makes compensationfor the angle offset, the trained FEQ coefficient may also be used toestimate the angle offset of each of the sinusoidal signals. Because theDMT frame synchronization may have an error, there may be offsetsbetween the angles obtained by the correcting module and the anglesobtained by the opposite apparatus. These offsets have a linearrelationship with frequencies of the sinusoidal signals, and a slope ofthe linear relationship directly reflects the frame synchronizationerror. Therefore, the correcting module can plot the offset of each ofthe sinusoidal signals on a coordinate system, and connect these offsetsinto a beeline, a slope of which is just the offset of the time stampsmade by the CPE due to the synchronization error. Affected by suchfactors as noises, these angle errors obtained through actualcalculation may not be strictly on a beeline. The CPE can calculate anoptimal beeline for approximation according to a certain optimizationalgorithm (for example, the least square method). The correcting modulecalculates the error of the CPE time stamp, and corrects the time Ts1′into the time Ts1 according to this error.

The correcting module may also reside on the communication apparatus,being independent of the receiving unit 400.

The receiving unit 400 may also receive, via a message, channelinformation transmitted by the second apparatus, including the time Tm2indicating the moment that the first symbol is received by the secondapparatus, the time Tm1 indicating the moment that the second symbol istransmitted by the second apparatus, and the transmission delay and thereception delay of the second apparatus. The transmission delay and thereception delay of the second apparatus include: a delay Δt1 of thedigital transmitting circuit, a delay Δt2 of the analog transmittingcircuit, a delay Δt5′ of the analog receiving circuit, and a delay Δt4′of the digital receiving circuit.

The second apparatus may also process the time Tm2 and the time Tm1 byusing the delay data of the second apparatus. In this way, the secondapparatus only needs to transmit the time Tm1 and the time Tm2 that areprocessed to the DSL apparatus; for example, Tm1=Tm1+Δt1+Δt2 orTm1=Tm1+Δt2, Tm2=Tm2−Δt5−Δt4 or Tm2=Tm2−Δt5.

The DSL apparatus may also process the time Ts1 and the time Ts2; i.e.,Ts1=Ts1−Δt1′−Δt2′ or Ts1=Ts1−Δt2′; Ts2=Ts2−Δt4′−Δt5′ or Ts2=Ts2−Δt5′.

The processing unit 600 obtains the delay of the DSL apparatus,calculates an offset between the clock of the local apparatus and theclock of the second apparatus according to the time Ts2 obtained by thetransmitting unit, Ts1, Tm2, Tm1 obtained by the receiving unit, and thedelay of the DSL apparatus, and adjusts the clock of the DSL apparatusaccording to the offset.

The delay of the DLS apparatus includes: a delay Δt1′ of the digitaltransmitting circuit, a delay Δt2′ of the analog transmitting circuit, adelay Δt5 of the analog receiving circuit and a delay Δt4 of the digitalreceiving circuit, all of which can be directly obtained when the DSLapparatus is delivered from the factory.

The processing unit 600 calculates the offset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt1+Δt2+Δt3+Δt1′+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt4+Δt5+Δt6+Δt5′+Δt4′)orOffset=Ts1−Tm1−Delay1=Ts1−Tm1−(Δt2+Δt3+Δt2′)Offset=Ts2−Tm2+Delay2=Ts2−Tm2+(Δt5+Δt6+Δt5′);or

the DSL apparatus and the second apparatus, after processing thetransmitted/received symbol, calculate the offset according to:Offset=Ts1−Tm1−Delay1=Ts1−Tm1−Δt3, andOffset=Ts2−Tm2+Delay1=Ts2−Tm2+Δt6.

The processing unit 600 reads the local clock time, and adjusts thelocal time according to the local clock time and the offset.

The second apparatus may be the CO or the CPE, and the DSL apparatus mayalso be used as the CO or the CPE.

As can be seen from the above embodiments, according to the presentinvention, by correcting the local time corresponding to the timestamps, the local time can be read by the receiver exactly, and theoffset between the clock of the CPE and the clock of the CO can becalculated so that the clock of the CPE can be adjusted according to theoffset to achieve synchronization between the clock of the CO and theclock of the CPE.

It can be understood by those of ordinary skill in the art that, all orpart of the steps in the methods of the above embodiments can beperformed by a program running on related hardware. The program can bestored in a computer-readable storage medium, including a read-onlymemory (ROM), a random access memory (RAM), a magnetic disk or a compactdisk (CD).

The above disclosure is only several embodiments of the presentinvention. However, the present invention is not only limited to theseembodiments, and any modifications that may occur for people skilled inthe art shall fall into the protection scope of the present invention.

What is claimed is:
 1. A method for time synchronization of a digitalsubscriber line (DSL), the method comprising: receiving, by a firstapparatus, a second symbol transmitted by a second apparatus, andobtaining a time Ts1 at which the second symbol is received by the firstapparatus; transmitting, by the first apparatus, a first symbol to thesecond apparatus, and obtaining a time Ts2 at which the first symbol istransmitted by the first apparatus; obtaining, by the first apparatus, atime Tm2 at which the first symbol is received by the second apparatusand a time Tm1 at which the second symbol is transmitted by the secondapparatus; calculating, by the first apparatus, an offset between aclock of the first apparatus and a clock of the second apparatusaccording to the time Ts1, the time Ts2, the time Tm1 and the time Tm2;adjusting, by the first apparatus, the clock of the first apparatus withthe offset to synchronize with the clock of the second apparatus; andobtaining a phase difference between a receiving point phase and a checkpoint phase, wherein the receiving point is a position where a signal ofthe second symbol is received by the first apparatus and the check pointis a position where the same signal of the second symbol is transmittedby the second apparatus; wherein the time Ts2 is a time at which asample at a starting position of the first symbol is transmitted by thefirst apparatus, the time Tm2 is a time at which the same sample at thestarting position of the first symbol is received by the secondapparatus, the time Tm1 is a time at which a sample at a startingposition of the second symbol is transmitted by the second apparatus,and the time Ts1 is a time at which the same sample at the startingposition of the second DMT symbol is received by the first apparatus,wherein the offset is calculated based on an assumption that adownstream propagation delay and an upstream propagation delay of atwisted pair of the DSL are approximately identical.
 2. The methodaccording to claim 1, further comprising: adjusting the time Tm1 byadding a delay produced by the second apparatus.
 3. The method accordingto claim 1, wherein the first symbol and the second symbol are discretemulti-tone (DMT) symbols.
 4. The method according to claim 1, whereinthe first apparatus is a customer premises equipment (CPE) and thesecond apparatus is a central office (CO) equipment.
 5. The methodaccording to claim 1, wherein the time Tm2 and the time Tm1 are sent tothe first apparatus via a message channel.
 6. The method according toclaim 1, wherein the time Ts1, the time Ts2, the time Tm1 and the timeTm2 are obtained at the first apparatus endpoint of a twisted pair orthe second apparatus endpoint of a twisted pair.
 7. A method for timesynchronization of a digital subscriber line (DSL), the methodcomprising: receiving, by a first apparatus, a second symbol transmittedby a second apparatus, and obtaining a time Ts1 at which the secondsymbol is received by the first apparatus; transmitting, by the firstapparatus, a first symbol to the second apparatus, and obtaining a timeTs2 at which the first symbol is transmitted by the first apparatus;obtaining, by the first apparatus, a time Tm2 at which the first symbolis received by the second apparatus and a time Tm1 at which the secondsymbol is transmitted by the second apparatus; calculating, by the firstapparatus, an offset between a clock of the first apparatus and a clockof the second apparatus according to the time Ts1, the time Ts2, thetime Tm1 and the time Tm2; and adjusting, by the first apparatus, theclock of the first apparatus with the offset to synchronize with theclock of the second apparatus; wherein the time Ts2 is a time at which asample at a starting position of the first symbol is transmitted by thefirst apparatus, the time Tm2 is a time at which the same sample at thestarting position of the first symbol is received by the secondapparatus, the time Tm1 is a time at which a sample at a startingposition of the second symbol is transmitted by the second apparatus,and the time Ts1 is a time at which the same sample at the startingposition of the second DMT symbol is received by the first apparatus,wherein the offset is calculated based on an assumption that adownstream propagation delay and an upstream propagation delay of atwisted pair of the DSL are approximately identical, wherein theobtaining by the first apparatus of the time Ts1 at which the secondsymbol is received comprises: reading, by the first apparatus, a timeTs1′ at which the first apparatus receives a signal of the secondsymbol; correcting, by the first apparatus, the time Ts1′ to the timeTs1 at which the first apparatus shall receive a check point accordingto a phase difference between a receiving point phase and a check pointphase, wherein the receiving point is a position where the signal of thesecond symbol is received by the first apparatus and the check point isa position where the signal of the second symbol is transmitted by thesecond apparatus; and obtaining, by the first apparatus, the time Ts1and using it as the time indicating the moment that the second symbol isreceived.
 8. The method according to claim 7, wherein the step ofcorrecting comprises: when a plurality of signals in the second symbolis used by the first apparatus, obtaining, by the first apparatus, aphase of a check point in each of the signals; obtaining, by the firstapparatus, a phase of a receiving point in each of the signals;calculating, by the first apparatus, time taken from the phase of thereceiving point to the phase of the check point in each of the signals,so as to obtain a plurality of time values; obtaining, by the firstapparatus, an offset between time marks made by the first apparatusaccording to the plurality of time values; and correcting, by the firstapparatus, the time Ts1′ to the time Ts1 according to the offset.
 9. Themethod according to claim 8, wherein the obtaining, by the firstapparatus, the time Tm2 at which the first symbol is received by thesecond apparatus comprises: reading, by the second apparatus, a timeTm2′ at which the second apparatus receives a signal of the firstsymbol; correcting, by the second apparatus, the time Tm2′ to the timeTm2 at which the second apparatus shall receive a check point accordingto a phase difference between the phase at a receiving point and a checkpoint, wherein the receiving point is a position where the signal of thefirst symbol is received by the second apparatus and the check point isa position where the signal of the first symbol is transmitted by thefirst apparatus; and obtaining, by the second apparatus, the time Tm2and using it as the time indicating the moment that the first symbol isreceived.
 10. The method according to claim 9, wherein the correcting,by the second apparatus, the time Tm2′ to the time Tm2 comprises: whenusing a plurality of signals in the first symbol, obtaining, by thesecond apparatus, a phase of a check point in each of the signals;obtaining, by the second apparatus, a phase of a receiving point in eachof the signals; calculating, by the second apparatus, time taken fromthe phase of the receiving point to the phase of the check point in eachof the signals, so as to obtain a plurality of time values; obtaining,by the second apparatus, an offset between time marks made by the secondapparatus according to the plurality of time values; and correcting, bythe second apparatus, the time Tm2′ to the time Tm2 according to theoffset.
 11. A digital subscriber line (DSL) apparatus, comprising: atransmitting unit configured to transmit a first symbol and obtain atime Ts2 at which the first symbol is transmitted; a receiving unitconfigured to: receive a second symbol transmitted by a network deviceand obtain a time Ts1 at which the second symbol is received; obtain atime Tm2 at which the first symbol is received by the network device anda time Tm1 at which the second symbol is transmitted by the networkdevice; and obtain a phase difference between a receiving point phaseand a check point phase, wherein the receiving point is a position wherea signal of the second symbol is received by the DSL apparatus and thecheck point is a position where the same signal of the second symbol istransmitted by the network device; and a processing unit configured to:calculate an offset between a clock of the DSL apparatus and a clock ofthe network device according to the time Ts1, the time Ts2, the timeTm1, and the time Tm2; and adjust the clock of the DSL apparatusaccording to the offset; wherein the time Ts2 is a time at which asample at a starting position of the first symbol is transmitted by theDSL apparatus, the time Tm2 is a time at which the same sample at thestarting position of the first symbol is received by the network device,the time Tm1 is a time at which a sample at a starting position of thesecond symbol is transmitted by the network device, and the time Ts1 isa time at which the same sample at the starting position of the secondsymbol is received by the DSL apparatus, wherein the offset iscalculated based on an assumption that a downstream propagation delayand an upstream propagation delay of a twisted pair of the DSL areapproximately identical.
 12. The DSL apparatus according to claim 11,wherein the time Ts1, the time Ts2, the time Tm1 and the time Tm2 areobtained at the DSL apparatus endpoint of a twisted pair or the networkdevice endpoint of a twisted pair.
 13. The DSL apparatus according toclaim 11, wherein the DSL apparatus is a customer premises equipment(CPE).
 14. A digital subscriber line (DSL) apparatus, comprising: atransmitting unit configured to transmit a first symbol and obtain atime Ts2 at which the first symbol is transmitted; a receiving unitconfigured to: receive a second symbol transmitted by a network deviceand obtain a time Ts1 at which the second symbol is received; and obtaina time Tm2 at which the first symbol is received by the network deviceand a time Tm1 at which the second symbol is transmitted by the networkdevice; and a processing unit configured to calculate an offset betweena clock of the DSL apparatus and a clock of the network device accordingto the time Ts1, the time Ts2, the time Tm1, and the time Tm2, andadjust the clock of the DSL apparatus according to the offset whereinthe time Ts2 is a time at which a sample at a starting position of thefirst symbol is transmitted by the DSL apparatus, the time Tm2 is a timeat which the same sample at the starting position of the first symbol isreceived by the network device, the time Tm1 is a time at which a sampleat a starting position of the second symbol is transmitted by thenetwork device, and the time Ts1 is a time at which the same sample atthe starting position of the second symbol is received by the DSLapparatus, wherein the offset is calculated based on an assumption thata downstream propagation delay and an upstream propagation delay of atwisted pair of the DSL are approximately identical, an obtaining modulereceives a signal of the second symbol, obtains a time Ts1′ of the clockof the DSL apparatus, and obtains the time Tm2 at which the first symbolis received by the second apparatus and the time Tm1 at which the secondsymbol is transmitted by the network device; and a correcting modulecorrects the time Ts1′ to the time Ts1 at which the obtaining moduleshall receive a check point according to a phase difference between areceiving point phase and a check point phase, wherein the receivingpoint is a position where the signal of the second symbol is received bythe obtaining module, the check point is a position where the signal ofthe second symbol is transmitted by the network device, and thecorrecting module obtains the time Ts1 and uses it as the timeindicating the moment that the second symbol is received by theobtaining module.
 15. The DSL apparatus according to claim 14, whereinthe step of correcting, by the correcting module, the time Ts1′ to thetime Ts1 comprises: when using a plurality of signals in the secondsymbol, obtaining, by the correcting module a phase of a check point ineach of the signals; obtaining, by the correcting module, a phase of areceiving point in each of the signals; calculating, by the correctingmodule, time taken from the phase of the receiving point to the phase ofthe check point in each of the signals, so as to obtain a plurality oftime values; obtaining, by the correcting module, an offset of the timeTs1′ obtained by the obtaining module according to the plurality of timevalues; and correcting, by the correcting module, the time Ts1′ to thetime Ts1 according to the offset.
 16. A non-transitory computer readablemedium that stores a computer program comprising computer executableinstructions that, when executed, cause a device to implement thefollowing: receiving a second symbol transmitted by a second apparatus,and obtaining a time Ts1 at which the second symbol is received;transmitting a first symbol to the second apparatus, and obtaining atime Ts2 at which the first symbol is transmitted from a firstapparatus; obtaining a time Tm2 at which the first symbol is received bythe second apparatus and a time Tm1 at which the second symbol istransmitted by the second apparatus; calculating an offset between aclock of the first apparatus and a clock of the second apparatusaccording to the time Ts1, the time Ts2, the time Tm1, and the time Tm2;adjusting the clock of the first apparatus with the offset tosynchronize with the clock of the second apparatus; and obtaining aphase difference between a receiving point phase and a check pointphase, wherein the receiving point is a position where a signal of thesecond symbol is received by the first apparatus and the check point isa position where a signal of the second symbol is received by the firstapparatus and the check point is a position where the same signal of thesecond symbol is transmitted by the second apparatus; wherein the timeTs2 is a time at which a sample at a starting position of the firstsymbol is transmitted by the first apparatus, the time Tm2 is a time atwhich the same sample at the starting position of the first symbol isreceived by the second apparatus, the time Tm1 is a time at which asample at a starting position of the second symbol is transmitted by thesecond apparatus, and the time Ts1 is a time at which the same sample atthe starting position of the second symbol is received by the firstapparatus, wherein the offset is calculated based on an assumption thata downstream propagation delay and an upstream propagation delay of atwisted pair of the DSL are approximately identical.